Electronic circuits, and in particular circuits that involve storing electronic states, are vulnerable to high-energy sub-atomic particles and electromagnetic radiation. Many high-altitude flight, outer space, military, and nuclear applications require that such vulnerability be reduced to an acceptable level. The techniques that are used to reduce the vulnerability of these circuits to the effects of radiation are generally referred to as radiation hardening. For the most part, radiation hardening involves employing special circuit designs, circuit layouts, the use of select materials, or any combination thereof to increase the robustness of the circuit. Long-term radiation effects that may impact the long-term functionality of the circuit are referred to as total ionizing dose (TID) effects and are often mitigated using special circuit layer techniques.
Another type of radiation effect that is becoming more of an issue is referred to a single event effect (SEE). When a high-energy particle passes through a semiconductor providing the electronic circuit, excess charge may be left in the semiconductor along the path through which the particle passes. If excess charge is left on or near a node that is charged to a level representing a desired logic state, the excess charge may change the level of charge at the node. The change in charge level may result in the node changing from the desired logic state to another logic state. For example, if an ionized particle of radiation passes through a bi-state storage node that is charged for a logic 1, excess electrons from the ionized particle may collect at the storage node and discharge the storage node to a charge level corresponding to a logic 0. The effect of the change in charge level of the storage node may result in a temporary transient, where the storage node returns to the charge level for a logic 1 and does not upset the overall output of the of the electronic circuit. This type of SEE is referred to as a single event transient (SET). If the effect of the change in charge level of the storage node completely changes the output of the circuit, where the output does not return to the proper state, a single event upset (SEU) is said to occur. Generally, SETs and SEUs are temporary, unlike TID effects, which are more permanent, long-term radiation effects.
Latches are frequently used circuits that include storage nodes and benefit from being hardened to radiation. Exemplary radiation hardened latches include the dual interlocked storage cell (DICE) latch and a classic temporal latch. A traditional DICE latch is illustrated in FIG. 1. The DICE latch includes two cross-coupled inverter latches formed from PMOS transistors T1-T4 and complementary NMOS transistors T5-T8. The first cross-coupled inverter latch is formed from transistors T1, T2, T5, and T6 while the second cross-coupled inverter latch is formed from transistors T3, T4, T7, and T8.
Notably, node X0 is formed where transistors T1 and T5 are coupled, node X1 is formed where transistors T2 and T6 are coupled, node X2 is formed when transistors T3 and T7 are coupled, and node X3 is formed where transistors T4 and T8 are coupled. Node X0 is coupled to the gate of transistor T2 as well as the gate of transistor T8. Node X1 is coupled to the gates of transistors T5 and T3. Node X2 is coupled to the gates of transistors T6 and T4. Node X3 is coupled to the gates of transistors T7 and T1, and provides the output Q of the DICE latch.
The traditional DICE latch has only two inputs, which are connected to nodes X0 and X2. These two inputs are represented as nodes M0 and M1, which are respectively coupled to nodes X0 and X2 through pass transistors T9 and T10. A clock signal, CLKb, controls when the values on nodes M0 and M1 are written to nodes X0 and X2. As illustrated, when the clock signal CLKb is asserted low, the values on nodes M0 and M1 are written to nodes X0 and X2.
Generally, node X0 is at the same state as node X2. Similarly, node X1 is at the same state as node X3, which is the opposite state of nodes X0 and X2. Accordingly, the output Q, which corresponds to node X3, is generally the opposite logic state that is stored on nodes X0 and X1.
To radiation harden the DICE latch, the nodes X0-X3 must be physically separated from each other to an extent that will prevent any two of the nodes X0-X3 from being hit by a single radiation particle. As such, if one of the nodes X0-X3 is struck by a radiation particle and as a result has its state changed, the remaining nodes X0-X3 will effectively override the state change at the affected node such that the output Q is at most subjected to a transient glitch. The overall state of the DICE latch is not upset. When the affected node X0-X3 changes state in response to being struck by the radiation particle, the remaining nodes X0-X3 will operate to restore the affected node X0-X3 to its proper state.
One of the drawbacks of the traditional DICE latch is that it is prone to capturing the wrong logic states if nodes M0 and M1 have the wrong logic state when the clock signal CLKb is asserted low and the DICE latch is in a transparent mode. Although the DICE latch is relatively compact and has been proven effective in mitigating SEUs, it is vulnerable to SETs while in a transparent mode. Accordingly, there is a need for a technique to provide radiation hardened DICE latches that are not vulnerable to SETs while in transparent modes.
A classic temporal latch is illustrated in FIG. 2. The temporal latch employs three redundant feedback paths that are separated in time by intentionally differing delays. As illustrated, the first feedback path corresponds to node N2, the second feedback path corresponds to the delay circuit D1 and node MDb, and the third feedback path corresponds to delay circuits D2 and D3 as well as node MDDb. The delay circuits D1, D2, and D3 each provide a fixed delay δ. Those skilled in the art will recognize that the delays provided by each of the delay circuits D1, D2, and D3 may be different from one another, but for the purposes of illustration they are assumed to each provide the same delay δ.
The inputs to the temporal latch are a data input D and a clock signal CLK. The data input D is passed through a pass gate formed by transistors T11 and T12 to a node N1. The logic state of node N1 is inverted by an inverter I1 and presented to the beginning of each of the three redundant feedback paths. Each of the three redundant feedback paths terminates a corresponding input of an inverting majority gate MG1. The basic functionality of a majority gate is to provide an output corresponding to that of the majority of the inputs.
An exemplary majority gate is depicted in FIG. 3. As illustrated, the majority gate has three inputs, input A, input B, and input C. The majority gate is formed from six PMOS transistors T15-T20 and six NMOS transistors T21-T26, which are arranged in three complementary inverter stacks. When any two or more of the inputs A, B, and C are a logic 1, at least one pair of series NMOS transistors T21-T26 are turned on and pull the output OUT to a logic 0. Similarly, when any two or more of the inputs A, B, and C are a logic 0, at least one pair of the PMOS transistors T15-T20 are turned on and pull the output OUT to a logic 1. For example, if inputs A and B are a logic 1 and input C is a logic 0, transistors T21 and T22 are turned on and the output OUT is pulled to a logic 0. The other two stacks that include transistors T23-T26 are not pulled to a logic 0, because transistors T24 and T26, which are driven by input C, are turned off. Although input C is a logic 0, this will not affect the output OUT.
Returning to FIG. 2, the majority gate MG1 will receive three inputs from the three feedback paths and provide an output that corresponds to the majority of the three inputs. For example, if two or three of the three inputs are a logic 0, the output will be a logic 1, because the majority gate illustrated is an inverting majority gate. Similarly, if two or three of the inputs were a logic 0, the output of the majority gate MG1 would be a logic 1. In essence, the majority gate MG1 will filter out those inputs that are not in line with the majority of inputs. The output of the majority gate MG1 is fed through a pass gate formed by transistors T13 and T14 back to node N1. Notably, the logic state of node M, which corresponds to the output of the majority gate MG1 or the logic state of the input D, is alternately passed to node N1 through the respective pass gates in response to the clock signal CLK or CLKb as inverted by inverter I2.
The temporal latch provides immunity to SETs in the following manner. If the input D temporarily transitions to the wrong logic state for a duration less than the delay δ, the resulting transient is passed to the majority gate MG1 through the three different feedback paths at different times. In particular, a delay of δ is provided between the transients that appear on the three feedback paths. Assuming the transient is less than the delay δ, the majority gate MG1 will only see the transient on one input at a time. Since there are three inputs, a transient on a minority input will not affect the output of the majority gate MG1. In other words, assuming the transient has a duration of less than the delay δ, two of the three feedback paths will always have the correct logic state and the output of the majority gate MG1 will be based on the correct logic states. The temporal latch basically filters out any transients on the input D where the transients have a duration less than the delay δ. In a similar fashion, the temporal latch will filter out transients appearing on the clock signal CLK or CLKb through the same overall feedback loop. In addition to addressing transients on the input D and the clock signal CLK, transients appearing in the feedback paths, such as along nodes N2, MDb, and MDDb, are filtered out as long as no two nodes are affected at the same time.
One drawback of the temporal latch is that it typically cannot handle simultaneous hits on multiple nodes in the feedback paths. Further drawbacks include not being able to provide immunity to SETs that last longer than the delay δ. Unlike the DICE latch of FIG. 1, the temporal latch tends to be quite large due to the number of transistors and other components required for the delay circuits D1, D2, and D3. Accordingly, there is a need for a latch that overcomes the deficiencies of the temporal latch while maintaining its benefits.